Microprocessors intended for graphics applications must be able to move pixel information between memory bit maps as quickly as possible. In situations where many pixels must be transferred to a bit map, the transfer may be speeded up by using a block-write feature. Typically, a block-write is created by associating a color register with each VRAM, filling the color register with bits to determine the desired color value of selected portions of the VRAM, and then using both the address bits of the VRAM as well as the data bus input to the VRAM to determine the locations within the VRAM where the color represented by the value in the color register will appear. This technique does not burden the data bus with multiple copies of the same pixel value and thus increases the available memory bandwidth, again speeding up data transfers.
The simplest application where the block-write can be used to advantage is the fill, which transfers the same pixel value into a defined area of memory. Also, some forms of data expansion are well suited to the application of block-write techniques. Thus, when a bit map is stored in compressed form the 1's and 0's can represent the presence or absence of a pixel and block-writes can be used to decompress the bit map. Typically, this sort of expansion is applied to character fonts which are often stored in compressed form to save memory.
Problems arise because memory accesses must be made in regular mode and in block-write mode via the same bus and they must be consistent such that data written (or read) in one mode must be able to be read (or written) in the other mode. This is a problem, since before data can be written to VRAMs in block-write mode, the bit order of the compressed representation of the data must be manipulated or swizzled relative to the regular mode access. This bit order change is necessary because typically the compressed data is stored with one bit representing each multibit display pixel in a specific order. The storage of these bits is serial with each bit representing a corresponding display point. For example, the first bit (bit 0) would represent pixel position one. The second bit (bit 1) would represent pixel position two and the third bit (bit 2) would represent pixel position three. Thus, the bits on the bus represent the pixel positions one for one, such that bus bit position zero would contain data for the first pixel while bus position three would contain data for the fourth pixel. However, because of the physical arrangement of the VRAMs where successive pixels are stored in different VRAM chips (or Units), the data must be reordered before presentation to the VRAMs. Consider the case where the VRAMs are four bits wide (four planes), the 32 bit bus would have bus positions 0-3 connected to the first VRAM which in turn can control bits 0-3 of the first pixel in a normal write situation. Thus, following this logic, compressed data in bus bit position 1 (the second position) which should be destined to control the second pixel will, in reality, unless something is done, end up being communicated to the second input of the first VRAM, which is associated with the ninth pixel and not the required second pixel. Thus, a bit order rearrangement is necessary when functioning in the block-write mode.
A further problem is encountered since the nature of a data swizzle appears to depend on the size of the pixel. Thus, on first viewing it appears that several different swizzle circuits must be available to accommodate a broad range of pixel sizes and VRAM configurations. However, this imposes severe hardware constraints on the system in terms of wasted chip area or proliferation of external multiplex logic.
Accordingly, a need exists in the art for a swizzle arrangement which allows for the efficient manipulation of data so as to accomplish block-writes in an economical manner.
A further need exists in the art for such a circuit which can be used for any size pixel or VRAM configuration.